The work on customer-specific specifications is set to INPUT and the specific design verification work is performed and OUTPUT is performed in the following languages.
Function specifications (English)
- Implementation specifications (English)
- RTL (Verilog)
- Verification strategy book (English)
- Table of verification entries (English)
Build verification environment (SystemVerilog / SVA / UVM / C / C ++)
Script verification (SystemVerilog / SVA / UVM / C / C ++)
Manual verification environment (English)
- Verification results report (in English)
The above can be performed without the assistance of other engineers to some extent
Requirement
* English skill: Intermediate English skills
+ Communication: Intermediate
+Reading: Intermediate - Can read and understand most sentences but slowly
+ Writing: Intermediate - Can write paragraphs in simple but slow sentences.
Must
- More than 3 years of experience working in the semiconductor industry
- Knowledge and skills: Prioritize design skills, Verilog
Intermediate English skills
Better
- SystemVerilog, SVA, UVM Methodology, C, SystemC, etc.
Working condition : Mon-Fri: 08h00 ~ 17h00
Benefit
- Working with Japanese experts can help you improve your ability to work
- International, challenging, and friendly working environment
- Salary for 13th month
- Full of social welfare under Vietnamese Labor Law (Insurance, annual leave, ...)
- Annual travel and team building activities
- 12 annual leave days and 3 paid summer holidays
- Training: Trained in soft and technical skills
...
[Vietnamese] Công ty VIỆC ƠI là công ty Tuyển dụng nhân sự thứ ba với 100% vốn của NHẬT BẢN với môi trường trẻ năng động, dễ thương và vô cùng thân thiện. Đây là nơi sẽ giúp bạn biết thêm nhiều kiến thức về nhân sự cũng như nâng cao các kỹ năng mềm của bản thân.
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